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Micron Technology DRAM SDRAM-DDR3L, Part #: MT53E256M32D2DS-053 AAT:B TR | Dynamic random access memory | DEX DEX Part #: B260-13-F | DEX

SKU: 4105717600

4.4
USD17.26 USD45.26

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Ships within 48 hours · Estimated delivery Aug 11 - Aug 16

Description

Part #: B260-13-F | DEX Features:  Guard Ring Die Construction for Transient Protection  Ideally Suited for Automated Assembly  Low Power-Loss

at >105°C to 125°C • 16 internal banks (x8): 4 groups of 4 banks each • 8 internal banks (x16): 2 groups of 4 banks each • 8n-bit prefetch architecture • Programmable data strobe preambles • Data strobe preamble training • Command/Address latency (CAL) • Multipurpose register READ and WRITE capability • Write leveling • Self refresh mode • Low-power auto self refresh (LPASR) • Temperature controlled refresh (TCR) • Fine granularity refresh • Self refresh abort • Maximum power saving • Output driver calibration • Nominal

Operating from a 5 V supply

Part #: BTS500851TMAATMA1 | DEX Features: • Overload protection • Current limitation • Short circuit protection • Over temperature protection • Over voltage protection (including load dump) • Clamp of negative voltage at output • Fast deenergizing of inductive loads 1) • Low ohmic inverse current operation • Diagnostic feedback with load current sense • Open load detection via current sense • Loss of Vbb protection2) • Electrostatic discharge (ESD) protection • Green product (RoHS compliant) • AEC qualified

ultra-low power Real-Time Clock (RTC) with separate battery supply

Micron Technology DRAM SDRAM-DDR3L, Part #: MT53E256M32D2DS-053 AAT:B TR | Dynamic random access memory | DEX DEX Part #: B260-13-F | DEXMicron Technology DRAM SDRAMMobile , Part #: MT53E256M32D2DS 053 AAT: B TR features: Ultra low voltage core and I O power supplies VDD1 = 1. 701. 95V; 1. 80V nominal VDD2 = 1. 061. 17V; 1. 10V nominal VDDQ = 1. 061. 17V; 1. 10V nominal or Low VDDQ = 0. 570. 65V; 0. 60V nominal Frequency range 213310 MHz (data rate range: 426620 Mb s pin) 16n prefetch DDR architecture 8 internal banks per channel for concurrent operation Single data rate CMD ADR entry

Exchange/Return Notes
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